1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and its reading method.
2. Related Art
The magnetoresistive random access memory (hereafter referred to as MRAM as well) formed of memory cells each having a magnetic tunnel junction (hereafter referred to as MTJ as well) has excellent features such as non-volatility, infinite rewriting withstand property and fast operation. Therefore, application thereof as a universal memory is expected. Since variation among memory cells is large, it is difficult to make the capacity large.
In the MRAM, variation of the resistance value among cells caused by the shape of the MTJ is large, and distribution of low resistance values and distribution of high resistance values overlap sometimes. If in this case the method of using a reference resistance value which is provided between the average value of the high resistance values and the average value of the low resistance values and which is common to a plurality of cells as a reference and comparing a resistance value read out with the reference resistance value is used, then read errors are generated.
As a method for reading states in cells varied in resistance value without using the reference resistance value in order to solve the problem, a method called self reference reading is disclosed in U.S. Pat. No. 6,317,376. In the self reference read method, a value read out first is compared with a value read out after writing is performed and a decision is made whether the resistance of the cell has changed. A series of read operations in the self reference read method includes a first step of reading of a selected memory cell, a second step of the writing logic “0” and then reading, a third step of the writing logic “1” and then reading, a fourth step of deciding the read out logic state on the basis of results of the first to third steps, and a fifth step of writing back the decided logic state. There is a problem that the read access time is long. By the way, the decision of the read out logic state is performed by generating a reference voltage from read out voltages of the logic “0” and the logic “1” obtained at the second and third steps and comparing the reference voltage with a voltage obtained by the reading at the first step.
As an example of solving the problem of the long read access time, a circuit which shortens the read access time by executing reading consecutively after writing predetermined state is disclosed in U.S. Pat. No. 6,842,366. In this circuit as well, however, a procedure for performing switch to the read operation after write operation of predetermined state is necessary. The problem of the long read access time remains.